Engineering (Hobby Time!!)

Hardware:

• SpaceWire (IEEE 1355) Verilog RTL
  
  Link interface, node, switching routers with up to 32 links and networks. Verilog Altera and Xilinx FPGA. Download the design document or contact me for the RTL and synthesis deliverables.
  
  
  • Supports flow control, wormhole routing, header deletion, virtual channels in network level
  • Supports path addressing, logical addressing and regional and logical addressing, interval labeling, group adaptive routing for packets, broadcast and multicast packets
  • Supports application level, exchange level and network level error handling and link error recovery Disconnect error, Parity error, Escape sequence error, Character sequence error, Credit error.
  • Maximum data signalling rate of 640 Mb/s
  • Time interface, encoder, decoder, receive clock recovery, buffering, autostart
• MD5 Message Digest Verilog RTL
  
  Fully implemented, flexible 32bits to 128bits data input, any bit length input stream up to 2^64-1, padding, generates 128bits MD5 output, speed optimized. Compiles in Altera and Xilinx FPGA. Runs up to 100Mhz on Stratix II. Needs cosmetic modifications to convert RTL for ASIC. VHDL version is also available but not tested completely. Download the design document or contact me for the RTL and synthesis deliverables.

Software:

Other: