CRC BCH CALCULATOR
Forward Error correction. Block codes and convolutional codes.
This page will calculate the crc lfsr coefficients and will generate Verilog RTL code or C source code.
Enter the polynomial coefficients MSB representing x
0 The coefficients should be in GF(2).
If the final polynomial is convolution of multiple polynomial such as BCH or Reed-Solomon, seperate each polynomial with a comma character.
Example:
For polynomial x
16 + x
15 + x
2 + 1 enter 10100000000000011
For polynomials x
7 + x
4 + x
1 + 1 and x
8 + x
6 + x
3 + 1 enter 11001001,100100101
The polynomials will be conved in GF(2). The convolved polynomial to be processed will be: x
15 + x
13 + x
12 + x
4 + 1
Data width is the input data width of the crc module. Number of bits to be processed in every clock/call.
If speed is checked data will be pre xored to reduce the number of logic levels. This will increase theresult latency by one clock. The module is still capable of processing data every clock.
Polynomial(s):
| Polynomial functions for common CRC's |
|---|
| CRC-16 | 0x8005 | x16 + x15 + x2 + 1 |
| CRC-CCITT | 0x1021 | x16 + x12 + x5 + 1 |
| CRC-DNP | 0x3D65 | x16 + x13 + x12 + x11 + x10 + x8 + x6 + x5 + x2 + 1 |
| CRC-32 | 0x04C11DB7 | x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1 |
