SpaceWire

(Links, nodes, routers and networks) Verilog / VHDL design for FPGA / ASIC

Copyright Levent Ozturk

(323) 988-0345

Version 1.0

31st May, 2003

THE FILE CONTENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.

IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

1 Introduction. 4

1.1 Features. 4

1.2 File Structure. 5

2 Functional Description. 6

3 Detailed Design. 7

3.1 Routing Switch. 7

3.2 Node. 8

3.3 Link Interface. 9

3.3.1 Credit Management 10

3.3.2 Error Handling and Recovery. 11

5 AC Characteristics. 14

6 Software Interface. 15

6.1 Generic Register Interface. 15

6.2 NiosII Avalon Interface. 15

7.4 Behavioral Models. 16

7.5 Simulator Settings. 16

8 Lab Verification. 17

8.1 Lab settings. 17

8.2 Test Cases. 17

9 References. 18

Figure 1 Sample SpaceWire Network. 4

Figure 2 SpaceWire Routing Switch Block Diagram.. 7

Figure 3 SpaceWire Node Block Diagram.. 9

Figure 4 SpaceWire Link Layer Block Diagram.. 10

Figure 5 SpaceWire Credit Management 11

1 Introduction

A SpaceWire network is made up of a number of links, nodes and routing switches.

The nodes are the sources and destinations of packets.

SpaceWire links provide the means for passing packets from one node to another. SpaceWire is a full-duplex, bidirectional, serial, point-to-point data link between nodes and routing switches. Every link encodes data using two differential signal pairs in each direction. That is a total of eight signal wires, four in each direction for each link. Electrical standard for links is defined as LVDS.

SpaceWire packets are variable length data with header including the destination address.

Figure 1 Sample SpaceWire Network

1.1 Features

The SpaceWire implementation;

· Supports routing switches with up to 32 links.

· Instantiates Altera or Xilinx (parameterized) libraries and can easily be converted other FPGA vendors or ASIC RTL.

· Instantiates LVDS drivers and receivers.

· Runs at frequency up to xxx MHz.

· Uses xxx LE in Altera xxx device for node and xxx for xxx link routing switch.

· Supports flow control, wormhole routing, header deletion, virtual channels in network level

· Supports path addressing, logical addressing and regional and logical addressing, interval labeling, group adaptive routing for packets

· Supports broadcast and multicast packets

· Supports application level, exchange level and network level error handling and link error recovery Disconnect error, Parity error, Escape sequence error, Character sequence error, Credit error.

· A local node can be connected to a router to achieve router-node functionality without using external LVDS links.

1.2 File Structure

2 Functional Description

The SCPS network has two entities. These are Switching routers and nodes. This section describes the functional description of these entities.

Nodes provide an interface to transmit and receive data from the SCPS network. There are credit management and error recovery functions implemented in the nodes.

Routing switches routs the received data to the destination ports. They maintain a routing table to map the destination addresses to the physical ports.

3 I/O Signal Descriptions

Table 1 SpaceWire Node I/O Signal Descriptions

Name	Direction	Description
reset	I	Global reset
clk	I	Global clock
tx_serial_clk	I	Fast Serial clock to be used in SERDES blocks
link_disabled	I	Configuration
Link_start	I	Configuration
Link_auto_start	I	Configuration
Time_master	I	Configures the node as Time master which sends ticks out
Time_tick_period[31:0]	I	Time tick period. Used when configured as master
Time_out[7:0]	O	Time value received within tick message
Tick_out	O	Tick Pulse
Tx_ready	O	Node is ready to transmit a character
Tx_write	I	A character is ready to transmit
Tx_ctl_flag	I	Control Flag to be transmitted along with data
Tx_data[7:0]	I	Transmit Data
Rx_data_buffer_write	O	Received character is ready.
Rx_data_buffer_ready	I	User is ready to receive a new character
Rx_ctl_flag	O	Received Control Flag
Rx_data[7:0]	O	Received data
Rx_clk	O	Receive clock. Extracted from din, sin pair.
Dout	O	Serial data output
Sout	O	Serial strobe output
Din	I	Serial data input
sin	I	Serial strobe input

4 Detailed Design

This section describes the implementation details of tee routing switch, node and sub modules.

4.1 Routing Switch

Routing switch can be configured to instantiate up to 32 links. It maintains a routing table which is configured by the Software.

The LVDS interface is instantiated outside the routing switch module to make the module more generic and independent of physical layers and vendor primitives. This also allows connecting a local node to any of the ports and turns this site to both a routing switch and a node.

Software can configured the routing switch as Tick master. In this case an internally generated Tick will be transmitted through all the ports. If not configured as Tick master, any received tick message will be distributed to all the other ports.

Figure 2 SpaceWire Routing Switch Block Diagram

The routing switch is implemented with no queueing, no switchin delay, distributed arbitration with priority scheduling.

There is no queuing algorithm. Each source port can be directly selected by each destination port.

The switching logic runs at low speed parallel data side clock domain with no switching delay. Short packets will not degrade the bandwidth. Header processing is achieved on the fly.

There is one scheduling algorithm for each destination port. Each destination port will decide which source port to schedule. If multiple source ports are waiting for a single destination port, the lowest numbered source port will be scheduled. If multiple destination port is enabled for a source port( load distribution), the lowest destination port will reserve the source port. If the destination port is busy, the next destination port that is enabled for a source port will reserve the source port.

Routing table is duplicated for each link and structured the same. Write address

4.2 Node

This module basically replicates the link interface module and serialisers determined by the number of links parameter.

Figure 4 SpaceWire Node Block Diagram

4.3 Link Interface

This module implements the full featured link layer. This module is generic and used both in node module and the switching router module.

The LVDS interface is instantiated outside the node module to make the module more generic and independent of physical layers and vendor primitives. This also allows connecting a local node to a routing switch internally.

The data interface is also generic and is used to interface the software in node, and connected to the routing switch matrix inside the routing switch.

The Link FSM module controls the entire link operation. It implements the state machine described in Chapter 8.5 Figure 20 and Annex B of SpaceWire Standard.

Figure 5 SpaceWire Link Layer Block Diagram

4.3.1 Credit Management

Credit management is achieved by using two counters in both TX and RX for each direction.

On the TX side, the credit counter is incremented by 8 for each FCT that is received from RX and decremented by 1 for each data transmitted. If credit count is less than 56 and FCT is received, a credit error is generated.

The RX credit count is implemented in the Link FSM module. The RX credit counter is decremented by 8 for each FCT that is transmitted from TX and incremented by 1 for each data received. The Link FSM sends FCTs to keep the credit count at 56. If the RX credit count is 0 and new data is received, a credit error is generated.

Figure 6 SpaceWire Credit Management

4.3.2 Error Handling and Recovery

The following errors are fully implemented.

· Link level errors

o RxErr

§ Disconnect Error

§ Parity Error

§ Escape Error

o Credit Error

o Character Sequence Error

· Network level errors

o Link error

o EEP received

o Invalid destination address

4.4 Resets

4.5 Interrupts

5 Resource Utilization

SpaceWire Node and routing switch I implemented in several FPGA and ASIC devices. The following tables provide typical utilization figures using standard synthesis tool for different SpaceWire configurations.

Table 2SpaceWire Node with 1 link resource utilization