General Information |
| This Document Release | Dec 10, 2016 |
| Company Name | Levent Ozturk |
| IP Name | SpaceWire |
| IP Part Number | |
| Current IP Revision Number | 6.2 |
| Current Revision Release Date | Dec 10, 2016 |
| First Revision Release Date | May 16, 2002 |
| Compliance | ECSS-E-ST-50-12C-Rev.1-DIR3_23Nov2015_ |
Deliverables |
| DO-254 Certifiable | Yes. Requirements and derived requirements, Traceability between requirements, documents, code, and test cases. Checklists, Reviews. |
| IP Formats available for purchase | Bitstream, Netlist, Source Code |
| Source Code Format(s) | Verilog |
| High-Level Model Included? | No |
| High-level Model Format(s) | |
| Integration Testbench Provided | Yes |
| Integration Testbench Format(s) | Verilog |
| Code Coverage Report Provided? | Yes |
| Functional Coverage Report Provided? | |
| Constraints File Provided? | Yes |
| Commercial Evaluation Board Available? | Yes |
| FPGA used on board | Zynq, Virtex 6, Stratix IV |
| Software Drivers Provided? | No |
| Driver OS Support | |
Implementation |
| FPGA Optimization Techniques | Yes |
| Code Optimized for Vendor? | Altera, Xilinx |
| Synthesis Software Tools Supported / version | XST |
| Static Timing Analysis Performed? | Yes |
| Standard IP Interface(s) Supported | No |
| Metadata Included? | |
Verification |
| Is a documented verification plan available? | Yes |
| Test Methodology | Random, Incremental, Directed, Corner cases, stress cases |
| Assertions | Yes |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | Yes |
| Timing Verification Report Available? | Yes |
| Simulators supported | Modelsim, Cadence NC-Sim |
Hardware Validation |
| Validated on FPGA | Altera Xilinx |
| Hardware validation platform used | Xilinx Zynq |
| Industry standard compliance testing passed | Yes |
| Specific compliance test Test date | |
| Are test results available? | |
Production Use by Customers |
| Number of successful Customer production projects | 2 |
| Can references be made available? | Yes |
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