MD 5 Hardware Implementation
MD5 is used in many applications, including GPG, Kerberos, TLS / SSL, Cisco type 5 enable passwords, and RADIUS.
The difficulty of creating two files with the same MD5 hash should be approximately 264
. The difficulty of creating a file with a specific MD5 hash should be approximately 2128
This document describes the MD5 message-digest algorithm implemented in Verilog / VHDL RTL for Hardware. The MD5 message-digest algorithm module takes as input a message of arbitrary length and produces as output a 128-bit "fingerprint" or "message digest" of the input. It provides a direct interface for other hardware modules and an additional CPU interface to communicate directly with the CPU.
More details on MD5 design document
verilog rtl hardware implementation is also available.
- RFC 1321 compliant.
- Available as fully synchronous Verilogand VHDL synthesizable RTL supporting major FPGA vendor libraries.
- Supports virtually unlimited data size in bit granularity.
- Supports input handshaking for interrupted data input.
- Supports variable input data width.
- Altera® Cyclone III, Stratix III
- Xilinx® Virtex
- Generic ASIC libraries
- Full Version.
Compiled RTL Simulation Model, Compliant with the Altera® Quartus II (IDE)
- Netlist Version
- Structural VHDL and Verilog Netlists
- RTL version
- VHDL or Verilog Core Source Code
- Synthesis Scripts
- Verification Testbench
- User Testbenches
- Modelsim Compatible
- VHDL and Verilog
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