Levent Ozturk

The Verilog Console Module

General Information

This Data was Current OnJuly 12, 2015
Company NameLevent Ozturk
IP NameThe Verilog Console
IP Part Number
Price$295
Current IP Revision Number1.2
Date Current Revision was ReleasedMay 10, 2015
Release Date of first VersionMay 16, 2014
Product guideThe Verilog Console Product guide 1.2

Key Features

Read/WriteSingle, bulk, or W/R combo
MonitorContinious reporting of register sets
Serial InterfaceUART, RS232, USB
Internal InterfaceConfigurable data size. EHB bus.
Functionality
  • ASCII to binary conversion
  • No vendor specific primitive is used reusable and portable to ASIC,
  • Very low latency,
  • Configurable data and address width
  • Configurable output data width,
  • Fully tested with automated testbench,

Supported Families

XilinxVirtex 6, Virtex 7
AlteraStratix 10

Production Use by Customers

Number of successful Customer production projects2
Can references be made available?Yes

Deliverables

VSIA Quality IP (QIP) checklist completed and available?
IP Formats available for purchaseBitstream, Netlist, Source Code
Source Code Format(s)Verilog
High-Level Model Included?No
High-level Model Format(s)
Integration Testbench ProvidedYes
Integration Testbench Format(s)Verilog
Code Coverage Report Provided?Yes
Functional Coverage Report Provided?
Constraints File Provided?Yes
Commercial Evaluation Board Available?Yes
FPGA used on boardVirtex 7, Stratix 10
Software Drivers Provided?No
Driver OS Support

Implementation

FPGA Optimization TechniquesYes
Code Optimized for Vendor?Altera, Xilinx
Synthesis Software Tools Supported / versionXST
Static Timing Analysis Performed?Yes
Standard IP Interface(s) SupportedNo
Metadata Included?

Resource Utilization

Number of Rounds
per clock		 Input
data width		 Output
data width		 Logic DSP RAM
Altera Xilinx
Virtex 6		 Altera Xilinx
Virtex 6		 Altera Xilinx
Virtex 6
1 8 32 2040 0 0 0 0
16 32 2040 0 0 0 0
32 32 2040 0 0 0 0
64 32 2040 0 0 0 0
8 64 2040 0 0 0 0
16 64 2040 0 0 0 0
32 64 2040 0 0 0 0
64 64 2040 0 0 0 0
2 8 32 0 0 0 0 0
16 32 0 0 0 0 0
32 32 0 0 0 0 0
64 32 0 0 0 0 0
8 64 0 0 0 0 0
16 64 0 0 0 0 0
32 64 0 0 0 0 0
64 64 0 0 0 0 0
4 8 32 0 0 0 0 0
16 32 0 0 0 0 0
32 32 0 0 0 0 0
64 32 0 0 0 0 0
8 64 0 0 0 0 0
16 64 0 0 0 0 0
32 64 0 0 0 0 0
64 64 0 0 0 0 0

Performance

Number of Rounds
per clock		 Input
data width		 Output
data width		 Maximum
Frequency		 Throughput Latency
Altera Xilinx
Virtex 6		 Altera Xilinx
Virtex 6		 Altera Xilinx
Virtex 6
1 8 32 277MHz 0 2.2Gbps 25 25
16 32 277MHz 0 4.4Gbps 25 25
32 32 277MHz 0 8.8Gbps 25 25
64 32 277MHz 0 17.2Gbps 25 25
8 64 277MHz 0 2.3Gbps 25 25
16 64 277MHz 0 4.6Gbps 25 25
32 64 277MHz 0 9.2Gbps 25 25
64 64 277MHz 0 18.4Gbps 25 25
2 8 32 0 0 0 13 13
16 32 0 0 0 13 13
32 32 0 0 0 13 13
64 32 0 0 0 13 13
8 64 0 0 0 13 13
16 64 0 0 0 13 13
32 64 0 0 0 13 13
64 64 0 0 0 13 13
4 8 32 0 0 0 7 7
16 32 0 0 0 7 7
32 32 0 0 0 7 7
64 32 0 0 0 7 7
8 64 0 0 0 7 7
16 64 0 0 0 7 7
32 64 0 0 0 7 7
64 64 0 0 0 7 7
  • Altera: LE.
  • Xilinx: part V7100 speed grade -1 is used. Slices, DSP48, system clock.

Interface

Verification

Is a documented verification plan available?Yes
Test MethodologyRandom, Incremental, Directed, Corner cases, stress cases
AssertionsYes
Coverage Metrics CollectedCode
Timing Verification Performed?
Timing Verification Report Available?Yes
Simulators supportedModelsim, Cadence NC-Sim

Hardware Validation

Validated on FPGAAltera, Xilinx
Hardware validation platform used
Industry standard compliance testing passed
Specific compliance test Test date
Are test results available?

License

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