Levent Ozturk

Verilog XML Parser

The Verilog XML Parser core provides a complete XML Parsing solution for hardware environment. This core consists of parsing, filtering, impairment, search and error detecting stages. All parameters can be changed on a file-by-file basis.

Key Features

  • Fully compliance XML parser, complete solution
  • Extensive filtering interface for selecting set of data out of the stream. Up to 8 level structured filtering on elements, attributes or content. Up to 1Kb pattern match on each item.
  • Insert, Drop, Impair, Report, Trigger actions on filtered data
  • Parameters can be changed dynamically
  • Supports different character sets including UTF-8
  • Serial and parallel (up to 8 bits) input options giving area versus speed tradeoff
  • Throughput of 8bit/clock
  • Buffering on input and output
  • Full range of handshake signals for easy insertion into data path
  • Compatible with FPGA or ASIC architectures.
  • Deliverables
    • Verilog
    • IP core, Maga Core
    • Test Benches
Online implementaion of the XML parser is also available. I use this in several FPGA projects. It helps reducing the resources and implementation and testing time and increasing the overall speed. I hope it helps to you too. Enjoy...

XML Parser
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Notes:
ASN.1 and JSON parsers for hardware are also available in Verilog or IP core.

Hardware XML Parser is tested on Xilinx virtex 7 and Alttera FPGAs.

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