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Fast RTL Register in every possible step. In FPGA registers come for free. Use them. Remeber: FPGA favors sequential logic ASIC favors combinatorial logic. Sometimes flops prevent optimisation of bigger combinatorial though. If unnecessarly clocked this might increase routing resource usage that may also cause congestion. As a general rule the shorter the code lines the less logic level they are which means faster achievable clock speeds. Also the number of tabs in a code line are an indirect indication of logic levels which would reduce the fmax. Keep in mind that you may over do registering which may preventing the packing of logic into single LUT which may cause additional routing and slower fmax. Register at I/Os.
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