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Protecting FPGAs from Power Analysis Leakage reduction: These techniques make the set or sequence of operations less dependent on the key or secret intermediates. Balancing techniques to reduce variation in the power consumption can also be employed, although using these methods on FPGAs may require extra care due to asymmetries within the routing infrastructure. The overall goal of leakage reduction strategies is to reduce the leakage signal-to-noise ratio, increasing the number of power measurements an adversary would require for a successful attack.
Noise introduction: These techniques add different types of noise into the power consumption measurements available to the attacker, reducing the leakage-signal to noise ratio. Noise can be generated in the amplitude domain (e.g., by consuming random amounts of power) or in the temporal domain (e.g., by randomizing operation timing). As with leakage reduction, these countermeasures increase the number of power traces required by an adversary.
Obfuscation: By keeping algorithms secret, the attacker is forced to perform reverse engineering along with power analysis. Such countermeasures typically do not provide any security once an adversary understands the operation of the obscure function, but can increase the initial effort required for an attack. Because the cost of subsequent attacks is not increased, obfuscation-based countermeasures should be used with caution, but still may be better than having no protection at all.
Incorporating randomness: These categories include a broad range of techniques for randomizing the data manipulated by the device in ways that still produce the correct result. For public key systems, techniques for masking or blinding of data and keys can be particularly effective. Similarly, for symmetric algorithms such as AES, techniques for masking intermediates and tables can be effective. These techniques force the attacker to employ more complex attacks, such as higher order DPA that requires a larger number of measurements.