SpaceWire IP Core
SpaceWire enables the reliable sending of data at high-speed over full-duplex, point-to-point, serial data communication links. The SpaceWire IP core supports port speeds up to 2 Gbps with full ECSS-E-ST-50-12C-Rev.1 (23Nov2015) compliance, which allows for a quick and tested way to add SpaceWire stack in to any project.
It was designed particularly for space missions, but the excellent performance makes it the ideal fit for additional high-throughput applications.
This IP core covers Signal level, Character level, Exchange level, Packet level, Network level.
Key Features & Benefits
The SpaceWire IP core complies with SpaceWire standard offering rich feature set.
- Parametrized support for all major FPGA vendors or ASIC RTL.
- System clock frequency up to 350 MHz.
- Signaling rates up to 2 Gbps per port.
- Flexible physical layer clock selection. Physical layer clock can be driven by the link layer clock or an independent clock.
- Independent transmit and receive data rates for each port allowing to connect any device.
- Single clock to achieve all data rates. No PLL configuration, unnecessary clock buffering or complex clocking analysis are required.
- Glitch free link speed change.
- Low latency.
- Low resource utilisation.
- Avaliable Verilog or VHDL RTL and test bench.
- DO-254 certifiable.
- Time-code and interrupt support at node and router switch.
- Redundant link interface support in a single node
- Routing switch with up to 32 links.
- Non-blcoking switch
- Flow control
- Path addressing, logical addressing, group adaptive routing, multicast routing, wormhole routing, header deletion
- Supports application level, exchange level and network level error handling and link error recovery Disconnect error, Parity error, Escape sequence error, Character sequence error, Credit error.
- Configurable node, router, switch, or combination modes.
- Time interface, encoder, decoder, receive clock recovery, buffering, autostart
Documents & Resources
The SpaceWire Tester built on the SpaceWire IP core offering all the feautures of the core. The Tester can transparently monitor, capture and filter the SpaceWire traffic, impair or add/drop spacewire data.
- Monitor the SpaceWire traffic transparently
- Capture data based on the direct triggers or armed by filter settings
- Filter based on the type, destination address or any Spacewire defined data fields
- Add Drop packets, FCTs, NULLs
- Error Injection. Inject parity erros or ESC errors.
- Analyze the captured data.
Live SpaceWire Demo
A two port router running on a Zynq FPGA is connected online for demonstartion of the capabilities of the product. The ports of the router are externally looped back. Live data can be monitored at SpaceWire Demo
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